// **************************************************************
// COPYRIGHT(c)2021, Xidian University
// All rights reserved.
//
// IP LIB INDEX :  
// IP Name      :      
// File name    :  
// Module name  :  
// Full name    :  
// Time         : 2021 
// Author       : Haoxiaofei 
// Email        : 1531804419@qq.com
// Data         : 
// Version      : V 1.0 
// 
// Abstract     :
// Called by    :  
// 
// Modification history
// -----------------------------------------------------------------
// 
// 
//
// *****************************************************************
`timescale 1ns / 1ps

`include "top_define.v"
module fp_class_top( 
			input  wire 		 clk 				,
			input  wire 		 rst_n 				,
            input  wire  [11:0]  ram_dp_cfg_register,
            input  wire  [ 9:0]  ram_2p_cfg_register,
            input wire [6:0] rf_2p_cfg_register ,
			//\u6570\u636e\u5e27\u4fe1\u606f	
			input  wire 		     pkt_sop 			,
			input  wire 		     pkt_eop 			,
			input  wire          pkt_dsav       	,
			input  wire [255:0]  pkt_data 			,
			input  wire 		     pkt_dval 			,
			input  wire [  4:0]  pkt_mod 			,  
			input wire  [  7:0]  src_node_id 		,  //\u67e5\u627e\u66f4\u65b0\u7ec4\u64ad\u8868\u7528
(*mark_debug = "true"*)			output wire 		     pkt_rdy 			,	//\u5206\u7ec4\u5904\u7406\u6a21\u5757\u63a5\u6536\u6570\u636e\u51c6\u5907\u4fe1\u53f7
			//ME1-ME6\u4e0eCPU\u63a5\u53e3
`ifndef NO_CPU_MODE
      input  wire [31:0]                np_cpu_wr_data              ,
      input  wire [16:0]                np_cpu_addr                 ,
      input  wire [ 1:0]     np_cpu_ram_ctr              ,
      output wire [31:0]                np_cpu_rd_data              ,
      output wire                       fp_class_rd_vld             ,
`else 
      input  wire [31:0]                np_cpu_wr_data              ,
      input  wire [16:0]                np_cpu_addr                 ,
      input  wire [ 1:0]     np_cpu_ram_ctr              ,
      output wire [31:0]                np_cpu_rd_data              ,
`endif

      output wire [9:0]   bus1_table_addr2            ,
      output wire [9:0]   bus1_table_ram_addr_convert ,
      output wire [71:0]  bus1_table_data2            ,
      output wire [71:0]  bus1_table_ram_data_convert ,
      output wire         bus1_table_wren2            ,
      output wire         bus1_table_ram_wr_en_convert,
      input  wire [9:0]   bus2_table_addr2            ,
      input  wire [9:0]   bus2_table_ram_addr_convert ,
      input  wire [71:0]  bus2_table_data2            ,
      input  wire [71:0]  bus2_table_ram_data_convert ,
      input  wire         bus2_table_wren2            ,
      input  wire         bus2_table_ram_wr_en_convert,
      input  wire [9:0]   bus3_table_addr2            ,
      input  wire [9:0]   bus3_table_ram_addr_convert ,
      input  wire [71:0]  bus3_table_data2            ,
      input  wire [71:0]  bus3_table_ram_data_convert ,
      input  wire         bus3_table_wren2            ,
      input  wire         bus3_table_ram_wr_en_convert,
      input  wire [9:0]   bus4_table_addr2            ,
      input  wire [9:0]   bus4_table_ram_addr_convert ,
      input  wire [71:0]  bus4_table_data2            ,
      input  wire [71:0]  bus4_table_ram_data_convert ,
      input  wire         bus4_table_wren2            ,
      input  wire         bus4_table_ram_wr_en_convert,
			//\u548c\u63a5\u6536\u8c03\u5ea6\u63a5\u53e3
			output wire 		 in_buf_val 		,
			output wire 		 multicast 			,
			input  wire 		 schedule_start 	,
			//\u548cframe_info_fifo\u7684\u63a5\u53e3
			output wire 		 frame_info_fifo_empty,
			input  wire 		 frame_info_fifo_rden,
			output wire [ 31:0]  frame_info_fifo_o	,

			//\u6570\u636e\u5e27\u9996\u90e8\u4fe1\u606f
			output wire [ 47:0]  mac_src_addr 		,
			output wire [ 47:0]  mac_des_addr 		,
			output wire [  7:0]  src_node_ido 		,
			output wire [128:0]  ip_src_addr 		,	//\u53f7\u9ad8\u4f4d\ufffd??1\u4ee3\u8868ipv6
			output wire [128:0]  ip_des_addr 		,
			input  wire 		     mem_que_rdy 		,  //\u961f\u5217\u7ba1\u7406\u521d\u59cb\u5316\u5b8c\u6bd5\uff08\u7f13\u5b58\u7ba1\u7406\u94fe\u8868\u7b49\uff09
			//\u603b\u7ebf\u7ebf\u63a5\u53e3	
			input  wire 		     trans_start 		,	//\u603b\u7ebf\u7ed9\u51fa\u7684\u603b\u7ebf\u6570\u636e\u901a\u8def\u53ef\u7528\u4fe1\u53f7
			input  wire 		     discard_start 		,
			output wire 		     trans_ready 		,
			output wire              frame_rd_end ,

			output wire [262:0]  bus_data_o 		,
			output wire 		     bus_data_val_o		,	//\u5206\u7ec4\u5904\u7406\u7ed9\u51fa\u7684\u6570\u636e\u6709\u6548\u4fe1\u53f7
			output wire 		     bus_data_end_o		,	//\u5206\u7ec4\u5904\u7406\u7ed9\u51fa\u7684\u603b\u7ebf\u6570\u636e\u642c\u79fb\u7ed3\u675f\u4fe1\u53f7
			output wire [ 10:0]  frame_len_bus 		,
			
			
			//\u63d2\u5165\u63a5\u53e3
            output wire          rx_rdy_insert     	,
            input  wire          rx_ff_sop_insert  	,
            input  wire          rx_ff_eop_insert  	,
            input  wire          rx_ff_dval_insert 	,
            input  wire          rx_ff_dsav_insert 	,
            input  wire [255:0]  rx_ff_data_insert 	,
            input  wire [  4:0]  rx_ff_mod_insert  	,


            input  wire          insert_empty      	,                       
            input  wire [  7:0]  des_node_id_insert	, //\u63d2\u5165\u5e27\u76ee\u7684\u8282\u70b9\u53f7
            input  wire [  2:0]  pri_insert        	,
			
			//\u6355\u83b7\u63a5\u53e3
			input  wire [ 15:0]  capture_eth_type  	,
            input  wire          capture_rdy       	, //\u6355\u83b7\u6a21\u5757\u4e0d\u5fd9\u4fe1\u53f7
            output wire [262:0]  capture_data_o    	,     
            output wire          capture_dval      	, //\u6355\u83b7\u5199\u6570\u636e\u6709\u6548\u4fe1\u53f7
            output wire          capture_en        	,
            output wire [ 10:0]  cpt_frame_len     	,  
`ifdef NO_CPU_MODE    
			//\u914d\u7f6e\u5355\u64ad\u8f6c\u53d1\u8868
          input  wire         uni_loopback_on_off,
	      input  wire         collision_detect_on_off,
	      output wire [31:0]  collision_port_1,
	      output wire [31:0]  collision_port_2,
	      output wire [31:0]  collision_mac_addr_1,
	      output wire [31:0]  collision_mac_addr_2,
	      output wire         collision_wren,

	      input  wire         broadcast_pkt_pass,
	      output wire         broadcast_pkt_ack,
	      input  wire         unknow_pkt_pass,
	      output wire         unknow_pkt_ack,
`endif
	      // //with uni_cam_module
	      output wire         unicam_busy,
`ifdef NO_CPU_MODE
	      output wire         CPU_unicam_wren,
	      output wire [11:0]  CPU_unicam_addr,
	      output wire [31:0]  CPU_unicam_din ,
	      input  wire [31:0]  CPU_unicam_dout,
          input  wire         CPU_unicam_live_val ,
          input  wire [31:0]  CPU_unicam_live_time,
`endif
	      //with receive_sch
	      input  wire [47:0]  mac_sour  ,
	      input  wire [47:0]  mac_dest  ,
	      input  wire [ 3:0]  port_sour ,
          input  wire         uni_addr_en,
	      output wire         unicam_init_done,
	      output wire [ 3:0]  uni_outport   ,
	      output wire         uni_outport_en,
	      output wire         uni_lookup_fail ,
`ifdef NO_CPU_MODE
    		//\u914d\u7f6e\u7ec4\u64ad\u8f6c\u53d1\u8868
    		input  wire         CPU_mulcam_wren		,
    		input  wire [ 31:0] CPU_mulcam_modify	,
    		input  wire [ 31:0] CPU_mulcam_group_mac,
    		input  wire [ 31:0] CPU_mulcam_member	,
    		input  wire         CPU_mulcam_rden		,
    		input  wire [ 11:0] CPU_mulcam_addr		,
    		output wire [ 31:0] CPU_mulcam_dout		,
`endif
        output wire         multi_busy      ,
        input  wire         multi_addr_en   ,
        output wire [  7:0] multi_outport   ,
        output wire         multi_outport_en,   
               //\u521d\u59cb\u5316\u5b8c\u6210
        output wire         multicam_init_done 
   );
//*******************
//DEFINE PARAMETER
//*******************
//Parameter(s)

//*********************
//INNER SIGNAL DECLARATION
//*********************
//REGS
//WIRES
wire 		 	action_pkt_en_o		;
wire      action_pkt_en     ;
wire [ 255:0]	mac_tx_data  		;
wire 			mac_tx_wren         ;
wire [   4:0]	mac_tx_mod     		;
wire 			mac_tx_sop          ;
wire 			mac_tx_eop          ;

wire [0:1023] 	phv_data_o			;
wire            phv_vector_rdy;

wire [  88:0]	action_pkt_o		;


 
(*mark_debug = "true"*) wire analyser_is_working_o;
(*mark_debug = "true"*) wire analyser_is_done_o;



wire [ 8:0] layend;
wire [ 8:0] layend_i;

wire [ 1:0] pkt_mod_ctl;//5.23 xym

////////////////////////////////////////
// Module instantiation
////////////////////////////////////////
pkt_analysis_top U_aly(
    .clk(clk),
    .rst_n(rst_n),
    .ram_2p_cfg_register(ram_2p_cfg_register),
    .pkt_sop_i(pkt_sop),
    .pkt_eop_i(pkt_eop),
    .pkt_mod_i(pkt_mod),
    .pkt_dval_i(pkt_dval),
    .pkt_data_i(pkt_data),
    .pkt_mod_ctl(pkt_mod_ctl),//5.23 xym
    //.pkt_analyser_error_o(pkt_analyser_error_o),
    .analyser_is_working_o(analyser_is_working_o),
    .analyser_is_done_o(phv_vector_rdy),
    .match_field(phv_data_o),
    .layend(layend_i)
    );
layend_fifo U_layend(
    .clock(clk),
    .rst_n(rst_n),
    .fifo_wen(phv_vector_rdy),
    .fifo_wdata(layend_i),
    .fifo_ren(action_pkt_en),
    .fifo_rdata(layend),
    .fifo_empty_rd(),
    .almost_full()
    );
//8ME\u5339\u914d\u6a21\u5757
CLASS_8ME_TOP U_CLASS_8ME_TOP(
    .rst_n 			  	(rst_n 			),
    .clk 		  		  (clk 			  ),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .ram_2p_cfg_register(ram_2p_cfg_register),
    //ME1-6\u4e0eCPU\u63a5\u53e3
    `ifndef NO_CPU_MODE
    .np_cpu_wr_data(np_cpu_wr_data),
    .np_cpu_addr   (np_cpu_addr   ),
    .np_cpu_ram_ctr(np_cpu_ram_ctr),
    .np_cpu_rd_data(np_cpu_rd_data),
	.class_8me_rd_vld(fp_class_rd_vld) ,
	`else 
	.np_cpu_wr_data(np_cpu_wr_data),
    .np_cpu_addr   (np_cpu_addr   ),
    .np_cpu_ram_ctr(np_cpu_ram_ctr),
    .np_cpu_rd_data(np_cpu_rd_data),
	`endif

    .pktheader_vector 	 (phv_data_o		),
    .vector_rdy       	 (phv_vector_rdy)	,

    .action_pkt_o  		   (action_pkt_o	),
    .action_pkt_en_o   	 (action_pkt_en_o),
    .me1_action_en_o_ff       (action_pkt_en  ),

    //ME7
    .bus1_table_addr2            (bus1_table_addr2            ),
    .bus1_table_ram_addr_convert (bus1_table_ram_addr_convert ),
    .bus1_table_data2            (bus1_table_data2            ),
    .bus1_table_ram_data_convert (bus1_table_ram_data_convert ),
    .bus1_table_wren2            (bus1_table_wren2            ),
    .bus1_table_ram_wr_en_convert(bus1_table_ram_wr_en_convert),
    .bus2_table_addr2            (bus2_table_addr2            ),
    .bus2_table_ram_addr_convert (bus2_table_ram_addr_convert ),
    .bus2_table_data2            (bus2_table_data2            ),
    .bus2_table_ram_data_convert (bus2_table_ram_data_convert ),
    .bus2_table_wren2            (bus2_table_wren2            ),
    .bus2_table_ram_wr_en_convert(bus2_table_ram_wr_en_convert),
    .bus3_table_addr2            (bus3_table_addr2            ),
    .bus3_table_ram_addr_convert (bus3_table_ram_addr_convert ),
    .bus3_table_data2            (bus3_table_data2            ),
    .bus3_table_ram_data_convert (bus3_table_ram_data_convert ),
    .bus3_table_wren2            (bus3_table_wren2            ),
    .bus3_table_ram_wr_en_convert(bus3_table_ram_wr_en_convert),
    .bus4_table_addr2            (bus4_table_addr2            ),
    .bus4_table_ram_addr_convert (bus4_table_ram_addr_convert ),
    .bus4_table_data2            (bus4_table_data2            ),
    .bus4_table_ram_data_convert (bus4_table_ram_data_convert ),
    .bus4_table_wren2            (bus4_table_wren2            ),
    .bus4_table_ram_wr_en_convert(bus4_table_ram_wr_en_convert),
    .mac_sour                (mac_sour),
    .port_sour               (port_sour),
    .mac_dest                (mac_dest),
    .uni_addr_en             (uni_addr_en),
    .uni_lookup_fail         (uni_lookup_fail),
    .uni_outport             (uni_outport),
    .uni_outport_en          (uni_outport_en),
    `ifdef NO_CPU_MODE
    .himac_loopback_on_off     (1'b0/*uni_loopback_on_off*/),  //\u56de\u73af\u4e0d\u5f00\u542f\uff0cMAC\u5730\u5740\u5b66\u4e60\u51b2\u7a81
    .broadcast_pkt_pass      (1'b1/*broadcast_pkt_pass*/),  //\u5e7f\u64ad\u5305\u8fc7\u6ee4--1\u8868\u793a\u8fc7\u6ee4
    .broadcast_pkt_ack       (broadcast_pkt_ack),
    .unknow_pkt_pass         (1'b1/*unknow_pkt_pass*/),  //\u672a\u77e5\u5305\u8fc7\u6ee4--1\u8868\u793a\u8fc7\u6ee4
    .unknow_pkt_ack          (unknow_pkt_ack),
    .collision_detect_on_off (1'b1/*collision_detect_on_off*/),  //\u51b2\u7a81\u68c0\u6d4b\u5f00\u542f
    .collision_port_1        (collision_port_1),
    .collision_port_2        (collision_port_2),
    .collision_mac_addr_1    (collision_mac_addr_1),
    .collision_mac_addr_2    (collision_mac_addr_2),
    .collision_wren          (collision_wren),
    //with 
    .CPU_unicam_wren         (CPU_unicam_wren ),
    .CPU_unicam_addr         (CPU_unicam_addr ),
    .CPU_unicam_din          (CPU_unicam_din  ),
    .CPU_unicam_dout         (CPU_unicam_dout ),
    .CPU_unicam_live_val     (CPU_unicam_live_val ),
    .CPU_unicam_live_time    (CPU_unicam_live_time),
    `endif
	.unicam_busy             (unicam_busy),
	//\u521d\u59cb\u5316\u5b8c\u6210
	.unicam_init_done        (unicam_init_done),
    //ME8 \u914d\u7f6e\u7ec4\u64ad\u8f6c\u53d1\u8868
    `ifdef NO_CPU_MODE
    .CPU_mulcam_wren        (CPU_mulcam_wren     ),
    .CPU_mulcam_modify      (CPU_mulcam_modify   ),   
    .CPU_mulcam_group_mac   (CPU_mulcam_group_mac), 
    .CPU_mulcam_member      (CPU_mulcam_member   ), 
    .CPU_mulcam_rden        (CPU_mulcam_rden     ), 
    .CPU_mulcam_addr        (CPU_mulcam_addr     ), 
    .CPU_mulcam_dout        (CPU_mulcam_dout     ),
    `endif 
    //\u63a5\u6536\u8c03\u5ea6--\u7ec4\u64ad\u8f6c\u53d1\u8868
    .multi_busy             (multi_busy          ),
    .multi_addr_en          (multi_addr_en       ),
    .multi_outport          (multi_outport       ),
    .multi_outport_en       (multi_outport_en    ),
    //\u521d\u59cb\u5316\u5b8c\u6807\u5fd7
    .multicam_init_done     (multicam_init_done  ),
    .pkt_mod_ctl            (pkt_mod_ctl         )//5.23, xym
    );


frame_process u_frame_process(
	   .clk 						      (clk				  	),
	   .rst_n 						    (rst_n					),
       .ram_2p_cfg_register             (ram_2p_cfg_register),
       .rf_2p_cfg_register             (rf_2p_cfg_register) ,
	   // output wire rd_rdy,	
	   //\u4e0emac\u6216\u62c6\u5e27\u6a21\u5757\u63a5\u53e3,\u7edf\u4e00\u4ee5mac\u7ed3\u5c3e	  
	   .rx_rdy_mac 				    (pkt_rdy			),   
	   .rx_ff_sop_mac 				(pkt_sop	    ),
	   .rx_ff_eop_mac 				(pkt_eop	    ),
	   .rx_ff_dval_mac				(pkt_dval	    ),
	   .rx_ff_dsav_mac				(pkt_dsav	    ),               
	   .rx_ff_data_mac 			  (pkt_data	    ),
	   .rx_ff_mod_mac 				(pkt_mod 	    ),
	   //.rx_ff_err_mac 				(             ),                 	  //*\u6682\u65f6\u65e0\u7528
	   .src_node_id_i_mac 		(src_node_id			),
	   //\u4e0e\u63d2\u5165\u6a21\u5757\u63a5\u53e3\uff0c\u7edf\u4e00\u4ee5insert\u7ed3\u5c3e	
	   .rx_rdy_insert			  	(rx_rdy_insert			),
	   .rx_ff_sop_insert			(rx_ff_sop_insert		),
	   .rx_ff_eop_insert			(rx_ff_eop_insert		),
	   .rx_ff_dval_insert			(rx_ff_dval_insert		),
	   .rx_ff_dsav_insert			(rx_ff_dsav_insert		),
	   .rx_ff_data_insert			(rx_ff_data_insert		),
	   .rx_ff_mod_insert			(rx_ff_mod_insert		),
	   .insert_empty				  (insert_empty			),
	   .des_node_id_insert 	  (des_node_id_insert 	),
	   .pri_insert_i 				  (pri_insert 			),
	   //\u548c\u8c03\u5ea6\u5668\u4e4b\u95f4\u7684\u63a5\u53e3	
	   .in_buf_val 				    (in_buf_val				),//\u8c03\u5ea6\u4fe1\u606f\u6709\u6548\u4fe1\u53f7
	   .multicast  				    (multicast				),//\u662f\u5426\u662f\u5e7f\u64ad\u5e27
	   .schedule_start 			  (schedule_start			),//\u8c03\u5ea6\u6a21\u5757\u7684\u5e94\u7b54\u4fe1\u53f7\uff0c\u8868\u793a\u4ee5\u4e0a\u5e27\u4fe1\u606f\u5df2\u88ab\u63a5\u6536\uff08\u8fde\u63a5\u8c03\u5ea6\u6a21\u5757wr_gnt\u4fe1\u53f7\uff09\uff0c\u7ef4\u6301\ufffd??\u5468\u671f\u9ad8\u7535\ufffd??
	   .frame_info_fifo_empty (frame_info_fifo_empty	),
	   .frame_info_fifo_rden 	(frame_info_fifo_rden	),
	   .frame_info_fifo_o 		(frame_info_fifo_o		),//\u66f4\u6539 by Hbing \u52a0\u51659bit\u6307\u5b9adevice i
	   .src_node_id 				  (src_node_ido			),//\u6e90\u8282\u70b9\u53f7
	   .mac_src_addr				  (mac_src_addr			),
	   .mac_des_addr				  (mac_des_addr			),
	   .ip_src_addr 				  (ip_src_addr			),
	   .ip_des_addr 				  (ip_des_addr			),
        //\u63d2\u5165\u5e27\u5e0c\u671b\u8fdb\u5165\u7684\u8282\u70b9\u53f7
	   .mem_que_rdy 				  (mem_que_rdy			),
	   //ME1\u63a5\u53e3 
	   .action_dval 				  (action_pkt_en_o		),//ME1\u8f93\u51fa\u4f7f\u80fd
	   .action_data 				  (action_pkt_o			),//\u5305\u64cd\u4f5c
     .layend                (layend),
	   //\u4e0e\u603b\u7ebf\u7684\u63a5\u53e3 
	   .trans_ready				    (trans_ready			),
	   .frame_rd_end                (frame_rd_end),
	   .trans_start 				  (trans_start			),//\u603b\u7ebf\u7ed9\u51fa\u7684\u603b\u7ebf\u6570\u636e\u901a\u8def\u53ef\u7528\u4fe1
	   .discard_start 				(discard_start),	 
	   .bus_data_o					  (bus_data_o				),
	   .bus_data_val_o 			  (bus_data_val_o			),//\u5206\u7ec4\u5904\u7406\u7ed9\u51fa\u7684\u6570\u636e\u6709\u6548\u4fe1\u53f7
	   .bus_data_end_o 			  (bus_data_end_o			),//\u5206\u7ec4\u5904\u7406\u7ed9\u51fa\u7684\u603b\u7ebf\u6570\u636e\u642c\u79fb\u7ed3\u675f\u4fe1\u53f7
	   .frame_len_bus 				(frame_len_bus			),
	   //\u4e0e\u6355\u83b7\u6a21\u5757\u7684\u63a5\u53e3
	   .eth_type					    (capture_eth_type		),//\u76f4\u63a5\u6355\u83b7\u5230CPU\u7684\u4ee5\u592a\u7f51\u5e27\u578b
	   .capture_rdy				    (capture_rdy	 		),//\u6355\u83b7\u6a21\u5757\u4e0d\u5fd9\u4fe1\u53f7
	   .capture_data_o				(capture_data_o	 		),
	   .capture_dval				  (capture_dval	 		),//\u6355\u83b7\u5199\u6570\u636e\u6709\u6548\u4fe1\u53f7
	   .cpt_en 					      (capture_en 	 		),
	   .cpt_frame_len 				(cpt_frame_len  		),
	   //end
    
	   .access_fail 			   	(1'b0					),
	   .in_buf_access_fail 		(						)
    );
//*********************
//MAIN CORE
//********************


endmodule

